module testbench;
  logic clk = 0, reset = 1;
  logic [31:0] x1;
  logic halted;
  rv32i_core dut(.clk(clk), .reset(reset), .x1(x1), .halted(halted));
  always #1 clk = ~clk;
  initial begin
    $dumpfile("trace.vcd"); $dumpvars(0, dut);
    #2 reset = 0;
    wait(halted);
    if (x1 !== 12) $fatal(1, "x1 mismatch: %0d", x1);
    $display("rtl functional trace: PASS x1=%0d", x1);
    $finish;
  end
endmodule