module rv32i_core(input logic clk, input logic reset, output logic [31:0] x1, output logic halted);
  logic [31:0] pc;
  always_ff @(posedge clk) begin
    if (reset) begin pc <= 0; x1 <= 0; halted <= 0; end
    else if (!halted) begin
      case (pc)
        0: begin x1 <= 7; pc <= 4; end       // addi x1,x0,7
        4: begin x1 <= x1 + 5; pc <= 8; end  // addi x1,x1,5
        default: halted <= 1;
      endcase
    end
  end
endmodule