IF: instruction register <- memory[PC]
ID: A/B <- registers[rs1/rs2]
EX ALU: result <- ALU(A,B/imm), next=WB
EX load/store: address <- A+imm, next=MEM
EX branch: compare A/B; PC <- selected next_pc, next=IF
MEM load: data <- memory[address], next=WB
MEM store: memory[address] <- B; PC <- next_pc, next=IF
WB: registers[rd != 0] <- result/data; PC <- next_pc, next=IF
Control names are a teaching description, not a generated RTL netlist.