| path | formula | delay_ps | destination |
| --- | --- | --- | --- |
| article05_reg_to_reg_alu | clk_to_q_max + mux + alu_4bit + setup | 250 | register |
| single_cycle_add | max(regs, control) + mux + alu_32bit; max(result, control) + wb_mux + setup | 660 | rd |
| single_cycle_lw | max(regs, imm, control) + mux + alu_32bit + dmem_read; max(mem, control) + wb_mux + setup | 920 | rd |
| single_cycle_sw | addr=max(regs, imm, control)+mux+alu_32bit; max(addr, store_data, control)+dmem_write | 825 | memory |
| single_cycle_branch_taken | max(target=PC/imm/control+mux+alu_32bit, select=max(regs+branch_cmp, control), pc_plus_4) + pc_mux + setup | 620 | pc |